For example, Patent Document 1 shows a configuration in which a first processor monitors an operation of a second processor, and the second processor generates an output signal to be transmitted to another unit and places the first processor in a power save mode. When the second processor places the first processor in the power save mode, the first processor becomes unable to monitor an operation of the second processor. Therefore, if an abnormality occurs in the second processor and the output signal becomes abnormal, there is a possibility that the abnormal output signal is transmitted to another unit.
A system of Patent Document 1 is provided with a flip-flop circuit that is reset by a signal from the second processor instructing the power save mode and that is set by a signal from the first processor indicating recovery from the power save mode. Furthermore, the system is provided with an AND gate, one input of which is the output of the flip-flop and the other input of which is an output signal from the second processor. Because of the flip-flop circuit and the AND gate, when the first processor is in the power save mode, the output signal from the second processor is interrupted and is prevented from being outputted to another unit.
Patent Document 1: Japanese Patent No. 4377463.
However, in Patent Document 1, the flip-flop circuits and the AND gate are used to interrupt the output signal from the second processor as described above. Therefore, a circuit configuration for interrupting the output signal is complicated and the cost may be high. This difficulty becomes remarkable as the output signals to be transmitted from the second processor to an outside increase.